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rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a lc 2 mos complete, 12-bit analog i/o system AD7868 ? analog devices, inc., 1996 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 functional block diagram ro dac ri dac dgnd AD7868 r r ro adc agnd clock r r 12-bit dac dac serial interface adc serial interface 12-bit adc dac 3v reference adc 3v reference track/hold v in v out ldac tfs tclk dt control rfs rclk dr clk convst v dd v ss features complete 12-bit i/o system, comprising: 12-bit adc with track/hold amplifier 83 khz throughout rate 72 db snr 12-bit dac with output amplifier 3 m s settling time 72 db snr on-chip voltage reference operates from 6 5 v supplies low power C 130 mw typ small 0.3" wide dip applications digital signal processing speech recognition and synthesis spectrum analysis high speed modems dsp servo control general description the AD7868 is a complete 12-bit i/o system containing a dac and an adc . the adc is a successive approximation type with a track-and-hold amplifier having a combined throughput rate of 83 khz. the dac has an output buffer amplifier with a settling time of 3 m s to 12 bits. temperature compensated 3 v buried zener references provide precision references for the dac and adc. interfacing to both the dac and adc is serial, minimizing pin count and giving a small 24-pin package size. standard control signals allow serial interfacing to most dsp machines. asyn- chronous adc conversion control and dac updating is made possible with the convst and ldac logic inputs. the AD7868 operates from 5 v power supplies, the analog in- put/output range of the adc/dac is 3 v. the part is fully specified for dynamic parameters such as signal-to-noise ratio and harmonic distortion as well as traditional dc specifications. the part is available in a 24-pin, 0.3" wide, plastic or hermetic dual -in-line package (dip) and in a 28-pin, plastic soic package. product highlights 1. complete 12-bit i/o system. the AD7868 contains a 12-bit adc with a track-and-hold amplifier and a 12-bit dac with output am plifier. also included are separate on-chip voltage references for the dac and the adc. 2. dynamic specifications for dsp users. in addition to traditional dc specifications, the AD7868 is specified for ac parameters including signal-to-noise ratio and harmonic distortion. these parameters along with im- portant timing parameters are tested on every device. 3. small package. the AD7868 is available in a 24-pin dip and a 28-pin soic package.
abt parameter version 1 version 1 version 1 units test conditions/comments dynamic performance 2 signal-to-noise ratio 3, 4 (snr) @ +25 c 70 72 70 db min v in = 10 khz sine wave, f sample = 83 khz t min to t max 70 71 70 db min typically 71.5 db for 0 < v in < 41.5 khz total harmonic distortion (thd) C78 C78 C76 db max v in = 10 khz sine wave, f sample = 83 khz typically 71.5 db for 0 < v in < 41.5 khz peak harmonic or spurious noise C78 C78 C76 db max v in = 10 khz sine wave, f sample = 83 khz typically 71.5 db for 0 < v in < 41.5 khz intermodulation distortion (imd) second order terms C78 C78 C76 db max fa = 9 khz, fb = 9.5 khz, f sample = 50 khz third order terms C80 C80 C78 db max fa = 9 khz, fb = 9.5 khz, f sample = 50 khz track/hold acquisition time 2 2 2 m s max dc accuracy resolution 12 12 12 bits minimum resolution 12 12 12 bits no missing codes are guaranteed integral nonlinearity 12 12 12 lsb typ integral nonlinearity 1 1 lsb max differential nonlinearity 0.9 0.9 0.9 lsb max bipolar zero error 5 5 5 lsb max positive gain error 5 5 5 5 lsb max negative gain error 5 5 5 5 lsb max analog input input voltage range 3 3 3 volts input current 1 1 1 ma max reference output 6 ro adc @ +25 c 2.99/3.01 2.99/3.01 2.99/3.01 v min/v max ro adc tc 25 25 25 ppm/ c typ ro adc tc 40 50 ppm/ c max reference load sensitivity ( d ro adc vs. d i) C1.5 C1.5 C1.5 mv max reference load current change (0 m aC500 m a), reference load should not be changed during conversion logic inputs ( convst , clk, control) input high voltage, v inh 2.4 2.4 2.4 v min v dd = 5 v 5% input low voltage, v inl 0.8 0.8 0.8 v max v dd = 5 v 5% input current, i in 10 10 10 m a max v in = 0 v to v dd input current 7 (control input only) 10 10 10 m a max v in = v ss to dgnd input capacitance, c in 8 10 10 10 pf max logic outputs dr, rfs outputs output low voltage, v ol 0.4 0.4 0.4 v max i sink = 1.6 ma, pull-up resistor = 4.7 k w rclk output output low voltage, v ol 0.4 0.4 0.4 v max i sink = 2.6 ma, pull-up resistor = 2 k w dr, rfs , rclk outputs floating-state leakage current 10 10 10 m a max floating-state output capacitance 8 15 15 15 pf max conversion time external clock 10 10 10 m s max internal clock 10 10 10 m s max the internal clock has a nominal value of 2.0 mhz power requirements for both dac and adc v dd +5 +5 +5 v nom 5% for specified performance v ss C5 C5 C5 v nom 5% for specified performance i dd 22 22 25 ma max cumulative current from the two v dd pins i ss 12 12 13 ma max cumulative current from the two v ss pins total power dissipation 170 170 190 mw max typically 130 mw notes 1 temperature ranges are as follows: a/b versions, C40 c to +85 c; t version, C55 c to +125 c. 2 v in = 3 v 3 snr calculation includes distortion and noise components. 4 snr degradation due to asynchronous dac updating during conversion is 0.1 db typ. 5 measured with respect to internal reference. 6 for capacitive loads greater than 50 pf a series resistor is required (see internal reference section). 7 tying the control input to v dd places the device in a factory test mode where normal operation is not exhibited. 8 sample tested @ +25 c to ensure compliance. specifications subject to change without notice. rev. b C2C AD7868Cspecifications (v dd = +5 v 6 5%, v ss = C5 v 6 5%, agnd = dgnd = 0 v, f clk = 2.0 mhz external. all specifications t min to t max- unless otherwise noted.) adc section
abt parameter version 1 version 1 version 1 units test conditions/comments dynamic performance 2 signal-to-noise ratio 3 (snr) @ +25 c 70 72 70 db min v out = 1 khz sine wave, f sample = 83 khz t min to t max 70 71 70 db min typically 71.5 db at +25 c for 0 < v out < 20 khz 4 total harmonic distortion (thd) C78 C78 C76 db max v out = 1 khz sine wave, f sample = 83 khz typically C84 db at +25 c for 0 < v out < 20 khz 4 peak harmonic or spurious noise C78 C78 C76 db max v out = 1 khz sine wave, f sample = 83 khz typically C84 db at +25 c for 0 < v out < 20 khz 4 dc accuracy resolution 12 12 12 bits integral nonlinearity 1/2 1/2 1/2 lsb typ integral nonlinearity 1 1 lsb max differential nonlinearity 0.9 0.9 0.9 lsb max guaranteed monotonic bipolar zero error 5 5 5 lsb max positive full-scale error 5 5 5 5 lsb max negative full-scale error 5 5 5 5 lsb max reference output 6 ro adc @ +25 c 2.99/3.01 2.99/3.01 2.99/3.01 v min/v max ro adc tc 25 25 25 ppm/ c typ ro adc tc 40 50 ppm/ c max reference load change ( d ro dac vs. d i) C1.5 C1.5 C1.5 mv max reference load current change (0C500 m a) reference input ri dac input range 2.85/3.15 2.85/3.15 2.85/3.15 v min/v max 3 v 5% input current 1 1 1 m a max logic inputs ( ldac , tfs , tclk, dt) input high voltage, v inh 2.4 2.4 2.4 v min v dd = 5 v 5% input low voltage, v inl 0.8 0.8 0.8 v max v dd = 5 v 5% input current, i in 10 10 10 m a max v in = 0 v to v dd input capacitance, c in 7 10 10 10 pf max analog input output voltage range 3 3 3 v nom dc output impedance 0.3 0.3 0.3 w typ short-circuit current 20 20 20 ma typ ac characteristics 7 voltage output settling-time settling time to within 1/2 lsb of final value positive full-scale change 3 3 3 m s max typically 2 m s negative full-scale change 3 3 3 m s max typically 2.5 m s digital-to-analog glitch impulse 10 10 10 nv secs typ dac code change all 1s to all 0s digital feedthrough 2 2 2 nv secs typ v in to v out isolation 100 100 100 db typ v in = 3 v, 41.5 khz sine wave power requirements as per adc section notes 1 temperature ranges are as follows: a/b versions, C40 c to +85 c; t version, C55 c to +125 c. 2 v out (pkCpk) = 3 v. 3 snr calculation includes distortion and noise components. 4 using external sample and hold. 5 measured with respect to ri dac and includes bipolar offset error. 6 for capacitive loads greater than 50 pf a series resistor is required (see internal reference section). 7 sample tested @ +25 c to ensure compliance. specifications subject to change without notice. ordering guide relative temperature accuracy package model range snr (lsb) option* AD7868an C40 c to +85 c 70 db 1/2 typ n-24 AD7868aq C40 c to +85 c 70 db 1/2 typ q-24 AD7868bn C40 c to +85 c 72 db 1 max n-24 AD7868bq C40 c to +85 c 72 db 1 max q-24 AD7868ar C40 c to +85 c 70 db 1/2 typ r-28 AD7868br C40 c to +85 c 72 db 1 max r-28 *n = plastic dip; q = cerdip; r = soic (small outline ic). dac section AD7868 C3C rev. b (v dd = +5 v 6 5%, v ss = C5 v 6 5%, agnd = dgnd = 0 v, ri dac = +3 v and decoupled as shown in figure 2, v out load to agnd; r l = 2 k w , c l = 100 pf. all specifications t min to t max unless otherwise noted.)
AD7868 C4C rev. b limit at t min , t max limit at t min , t max parameter (a, b versions) (t version) units conditions/comments adc timing t 1 50 50 ns min convst pulse width t 2 3 440 440 ns min rclk cycle time, internal clock t 3 100 100 ns min rfs to rclk falling edge setup time t 4 20 20 ns min rclk rising edge to rfs 100 100 ns max t 5 4 155 155 ns max rclk to valid data delay, c l = 35 pf t 6 4 4 ns min bus relinquish time after rclk 100 100 ns max t 13 5 2 rclk +200 to 2 rclk +200 to ns typ convst to rfs delay 3 rclk + 200 3 rclk + 200 dac timing t 7 50 50 ns min tfs to tclk falling edge t 8 75 100 ns min tclk falling edge to tfs t 9 6 150 200 ns min tclk cycle time t 10 30 40 ns min data valid to tclk setup time t 11 75 100 ns min data valid to tclk hold time t 12 40 40 ns min ldac pulse width notes 1 timing specifications are sample tested at +25 c to ensure compliance. all input signals are specified with tr = tf = 5 ns (10% to 90% of 5 v) and timed from a voltage level of 1.6 v. 2 serial timing is measured with a 4.7 k w pull-up resistor on dr and rfs and a 2 k w pull-up resistor on rclk . the capacitance on all three output is 35 pf. 3 when using internal clock, rclk mark/space ratio (measured from a voltage level of 1.6 v) range is 40/60 to 60/40. for external clock, rclk mark/space ratio = external clock mark/space ratio. 4 dr will drive higher capacitance loads but this will add to t 5 since it increases the external rc time constant (4.7 k w /c l ) and hence the time to reach 2.4 v. 5 time 2 rclk to 3 rclk depends on conversion start to adc clock synchronization. 6 tclk mark/space ratio is 40/60 to 60/40. timing characteristics 1, 2 warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD7868 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. absolute maximum ratings* (t a = +25 c unless otherwise noted) v dd to agnd . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +7 v v ss to agnd . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 v to C7 v agnd to dgnd . . . . . . . . . . . . . . . . . C0.3 v to v dd +0.3 v v out to agnd . . . . . . . . . . . . . . . . . . . . . . . . . . . v ss to v dd v in to agnd . . . . . . . . . . . . . . . . v ss C0.3 v to v dd + 0.3 v ro adc to agnd . . . . . . . . . . . . . . . C0.3 v to v dd + 0.3 v ro dac to agnd . . . . . . . . . . . . . . . C0.3 v to v dd + 0.3 v ri dac to agnd . . . . . . . . . . . . . . . C0.3 v to v dd + 0.3 v digital inputs to agnd . . . . . . . . . . . C0.3 v to v dd + 0.3 v digital outputs to agnd . . . . . . . . . . C0.3 v to v dd + 0.3 v operating temperature range a, b versions . . . . . . . . . . . . . . . . . . . . . . . C40 c to +85 c t version . . . . . . . . . . . . . . . . . . . . . . . . . C55 c to +125 c storage temperature range . . . . . . . . . . . . C65 c to +150 c lead temperature (soldering, 10 secs) . . . . . . . . . . . +300 c power dissipation (any package) to +75 c . . . . . . . . 450 mw derates above +75 c by . . . . . . . . . . . . . . . . . . . . 10 mw/ c *stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. dip ro adc dgnd tclk dt ri dac agnd control clk rclk dr dgnd agnd ro dac nc v dd nc = no connect 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 10 11 12 9 AD7868 top view (not to scale) convst rfs v ss v out v in tfs ldac v dd v ss soic ro adc dgnd tclk dt ri dac agnd control clk rclk dr dgnd agnd ro dac nc v dd nc = no connect 1 7 8 9 24 23 22 21 20 19 18 17 16 15 14 12 13 AD7868 top view (not to scale) convst rfs v ss v out v in tfs ldac 10 11 3 4 5 6 2 28 27 26 25 nc nc nc nc v dd v ss pin configurations (v dd = +5 v 6 5%, v ss = C5 v 6 5%, agnd = dgnd = 0 v)
AD7868 C5C rev. b pin function description dip pin number mnemonic function power supply 7 & 23 v dd positive power supply, 5 v 5%. both v dd pins must be tied together. 10 & 22 v ss negative power supply, C5 v 5%. both v ss pins must be tied together. 8 & 19 agnd analog ground. both agnd pins must be tied together. 6 &17 dgnd digital ground. both dgnd pins must be tied together. analog signal and reference 21 v in adc analog input. the adc input range is 3 v. 9v out analog output voltage from dac. this output comes from a buffer amplifier. the range is bipolar, 3 v with ri dac = +3 v. 20 ro adc voltage reference output. the internal adc 3 v reference is provided at this pin. this output may be used as a reference for the dac by connecting it to the ri dac input. the external load capability of this reference is 500 m a. 11 ro dac dac voltage reference output. this is one of two internal voltage references. to operate the dac with this internal reference, ro dac should be connected to ri dac. the external load capability of the reference is 500 m a. 12 ri dac dac voltage reference input. the voltage reference for the dac must be applied to this pin. it is internally buffered before being applied to the dac. the nominal reference voltage for correct operation of the AD7868 is 3 v. adc interface and control 2 clk clock input. an external ttl-compatible clock may be applied to this input. alternatively, tying pin to v ss enables the internal laser-trimmed oscillator. 3 rfs receive frame synchronization, logic output. this is an active low open-drain output which provides a framing pulse for serial data. an external 4.7 k w pull-up resistor is required on rfs . 4 rclk receive clock, logic output. rclk is the gated serial clock output which is derived from the internal or external adc clock. if the control input is at v ss the clock runs continuously. with the control input at dgnd the rclk output is gated off (three-stated) after serial transmission is complete. rclk is an open-drain output and requires an external 2 k w pull-up resistor. 5 dr receive data, logic output. this is an open-drain data output used in conjunction with rfs and rclk to transmit data from the adc. serial data is valid on the falling edge of rclk when rfs is low. an external 4.7 k w resistor is required on the dr output. 1 convst convert start, logic input. a low to high transition on this input puts the track-and-hold amplifier into the hold mode and starts an adc conversion. this input in asynchronous to the clk input. 24 control control, logic input. with this pin at 0 v, the rclk is noncontinuous. with this pin at C5 v, the rclk is continuous. note, tying this pin to v dd places the part in a factory test mode where normal operation is not exhibited. dac interface and control 14 tfs transmit frame synchronization, logic input. this is a frame or synchronization signal for the dac with serial data expected after the falling edge of this signal. 15 dt transmit data, logic input. this is the data input which is used in conjunction with tfs and tclk to transfer serial data to the input latch. 16 tclk transmit clock, logic input. serial data bits are latched on the falling edge of tclk when tfs is low. 13 ldac load dac, logic input. a new word is transferred into the dac latch from the input latch on the falling edge of this signal. 18 nc no connect.
AD7868 C6C rev. b converter details the AD7868 is a complete 12-bit i/o port, the only external components required for normal operation are pull-up resistors for the adc data outputs and power supply decoupling capaci- tors. it is comprised of a 12-bit successive approximation adc with a track/hold amplifier, a 12-bit dac with a buffered output and two 3 v buried zener references, a clock oscillator and con- trol logic. adc clock the AD7868 has an internal clock oscillator which can be used for the adc conversion procedure. the oscillator is enabled by tying the clk input to v ss . the oscillator in laser trimmed at the factory to give a conversion time of between 8.5 and 10 m s. the mark/space ratio can vary from 40/60 to 60/40. alterna- tively, an external ttl compatible clock may be applied to this input. the allowable mark/space ratio of an external clock is 40/60 to 60/40. rclk is a clock output, used for the serial in- terface. this output is derived directly from the adc clock source and can be switched off at the end of conversion with the control input. adc conversion timing the conversion time for both external clock and continuous in- ternal clock can vary from 19 to 20 rising clock edges depending on the conversion start to adc clock synchronization. if a con- version is initiated within 30 ns prior to a rising edge of the adc clock, the conversion time will consist of 20 rising clock edges, i.e., 9.5 m s conversion time. for noncontinuous internal clock, the conversion time is always 19 rising clock edges. adc track-and-hold amplifier the track-and-hold amplifier on the analog input of the AD7868 allows the adc to accurately convert an input sine wave of 6 v peakCpeak amplitude to 12-bit accuracy. the input impedance is typically 9 k w , an equivalent circuit is shown in figure 1. the input bandwidth of the track/hold amplifier is much greater than the nyquist rate of the adc, even when the adc is operated at its maximum throughput rate. the 0.1 db cutoff frequency oc- curs typically at 500 khz. the track/hold amplifier acquires an input signal to 12-bit accuracy in less than 2 m s. AD7868* 4.5k w *additional pins omitted for clarity v in to internal comparator track/hold amplifier to internal 3v reference 4.5k w figure 1. adc analog input the overall throughput rate is equal to the conversion time plus the track/hold amplifier acquisition time. for a 2.0 mhz input clock the throughput time is 12 m s max. the operation of the track/hold amplifier is essentially transpar- ent to the user. the track/hold amplifier goes from its track mode to its hold mode at the start of conversion on the rising edge of convst . internal references the AD7868 has two on-chip temperature compensated buried zener references which are factory trimmed to 3 v 10 mv. one reference provides the appropriate biasing for the adc, while the other is available as a reference of the dac. both ref- erence outputs are available (labeled ro dac and ro adc) and are capable of providing up to 500 m a to an external load. the dac input reference (ri dac) can be stored externally or connected to any of the two on-chip references. applications requiring good full-scale error matching between the dac and the adc should use the adc reference as shown in figure 4. the maximum recommended capacitance on either of the refer- ence output pins for normal operation is 50 pf. if either of the reference outputs is required to drive a capacitive load greater than 50 pf, then a 200 w resistor must be placed in series with the capacitive load. the addition of decoupling capacitors, 10 m f in parallel with 0.1 m f, as shown in figure 2, improves noise performance. the improvement in noise performance can be seen from the graph in figure 3. note, this applies for the dac output only; reference decoupling components do not af- fect adc performance. so, a typical application will have just the dac reference source decoupled with the other one open circuited. ri dac 200 w 10 m f 0.1 m f ro dac or ro adc* ext load greater than 50pf *ro dac/ro adc can be left open circuit if not used figure 2. reference decoupling circuitry dac output amplifier the output from the voltage-mode dac is buffered by a nonin- verting amplifier. the buffer amplifier is capable of developing 3 v across 2 k w and 100 pf load to ground and can produce 6 v peak-to-peak sine wave signals to a frequency of 20 khz. the output is updated on the falling edge of the ldac input. the output voltage settling time, to within 1/2 lsb of its final value, is typically less than 2 m s. the small signal (200 mv p-p) bandwidth of the output buffer amplifier is typically 1 mhz. the output noise from the ampli- fier is low with a figure of 30 nv/ ? hz at a frequency of 1 khz. the broadband noise from the amplifier exhibits a typical peak- to-peak figure of 150 m v for a 1 mhz output bandwidth. fig- ure 3 shows a typical plot of noise spectral density versus fre- quency for the output buffer amplifier and for either of the on-chip references.
AD7868 C7C rev. b 500 200 100 50 20 10 50 100 200 1k 2k 10k 20k 100k frequency ?hz nv ? ? hz ref out dac output with all 0s loaded ref out decoupled as shown in figure 2 t a = +25 c v dd = +5v v ss = ?v figure 3. noise spectral density vs. frequency input/output transfer functions a bipolar circuit for the AD7868 is shown in figure 4. the ana- log input/output voltage range of the AD7868 is 3 v. the de- signed code transitions for the adc occur midway between successive integer lsb values (i.e., 1/2 lsb, 3/2 lsb, 5/2 lsb . . . fs C 3/2 lsbs). the input/output code is 2s complement binary with 1 lsb = fs/4096 = 1.46 mv. the ideal transfer function is shown in figure 5. AD7868* ro adc ri dac agnd *additional pins omitted for clarity v in v out analog output range = ?v analog input range = ?v r1 200 c2 0.1? c1 10? figure 4. AD7868 basic bipolar operation using ro adc as a reference input for the dac -fs 2 fs = 6v 1lsb = fs 4096 0v 011...111 011...110 000...010 000...001 000...000 111...111 111...110 100...001 100...000 input voltage output code 2 -1lsb fs + figure 5. AD7868 input/output transfer function offset and full-scale adjustment in most digital signal processing (dsp) applications, offset and full-scale errors have little or no effect on system performance. offset error can always be eliminated in the analog domain by ac coupling. full-scale errors do not cause problems as long as the input signal is within the full dynamic range of the adc. for applications which require that the input signal range match the full analog input dynamic range of the adc, offset and full-scale errors have to be adjusted to zero. adc adjustment figure 6 has signal conditioning at the input and output of the AD7868 for trimming the end points of the transfer functions of both the adc and the dac. offset error must be adjusted be- fore full-scale error. for the adc, this is achieved by trimming the offset of a1 while the input voltage, v1, is 1/2 lsb below ground. the trim procedure is as follows: apply a voltage of C0.73 mv (C1/2 lsb) at v1 in figure 6 and adjust the offset voltage of a1 until the adc output code flickers between 1111 1111 1111 (fff hex) and 0000 0000 0000 (000 hex). adc gain error can be adjusted at either the first code transi- tion (adc negative full scale) or the last code transition (adc positive full scale). the trim procedures for both cases are as follows (see figure 6). adc positive full-scale adjustment apply a voltage of 2.9978 v (fs/2 C 3/2 lsbs) at v1. adjust r2 until the adc output code flickers between 0111 1111 1110 (7fe hex) and 0111 1111 1111 (7ff hex). adc negative full-scale adjustment apply a voltage of C2.9993 v (Cfs/2 + 1/2 lsb) at v1 and adjust r2 until the adc output code flickers between 1000 0000 0000 (800 hex) and 1000 0000 0001 (801 hex). dac adjustment op amp a2 is included in figure 6 for the dac transfer func- tion adjustment. again offset must be adjusted before full scale. to adjust offset: load the dac with 0000 0000 0000 (000 hex) and trim the offset of a2 to 0 v. as with the adc adjust- ment, gain error can be adjusted at either the first code transi- tion (dac negative full scale) or the last code transition (dac positive full scale). the trim procedures for both cases are as follows: dac positive full-scale adjustment load the dac with 0111 1111 1111 (7ff hex) and adjust r7 until the op amp output voltage is equal to 2.9985 v, (fs/2 C 1 lsb). dac negative full-scale adjustment load the dac with 1000 0000 0000 (800 hex) and adjust r7 until the op amp output voltage is equal to 3.0 v (Cfs/2). AD7868* *additional pins omitted for clarity agnd a1 v1 input voltage range = 3v r1 10k r2 500 r3 10k r5 10k r4 10k v in v out a2 r6 10k r7 500 r8 10k r10 10k r9 10k v0 output voltage range = 3v figure 6. AD7868 with input/output adjustment
AD7868 C8C rev. b timing and control communication with the AD7868 is managed by 6 dedicated pins. these consist of separate serial clocks, word framing or strobe pulses and data signals for both receiving and transmit- ting data. conversion starts and dac updating are controlled by two digital inputs; convst and ldac . these inputs can be asserted independently of the microprocessor by an external timer when precise sampling intervals are required. alterna- tively, the ldac and convst can be driven from a decoded address bus allowing the microprocessor control over conversion start and dac updating as well as data communication to the AD7868. adc timing conversion control is provided by the convst input. a low to high transition on convst input starts conversion and drives the track/hold amplifier into its hold mode. serial data then be- comes available while conversion is in progress. the correspond- ing timing diagram is shown in figure 7. the word length is 16 bits; 4 leading zeros, followed by the 12-bit conversion result starting with the msb. the data is synchronized to the serial clock output (rclk) and is framed by the serial strobe ( rfs ). data is clocked out on a low to high transition of the serial clock and is valid on the falling edge of this clock while the rfs out- put is low. rfs goes low at the start of conversion and the first serial data bit (which is the first leading zero) is valid on the first falling edge of rclk. all the adc serial lines are open-drain outputs and require external pull-up resistors. the serial clock out is derived from the adc master clock source which may be internal or external. normally, rclk is required during the serial transmission only. in these cases it can be shut down (i.e., placed into high impedance) at the end of conversion to allow multiple adcs to share a common serial bus. however, some serial systems (e.g., tms32020) require a serial clock which runs continuously. both options are available on the AD7868 adc. with the control input at 0 v, rclk is noncontinuous and when it is at C5 v, rclk is continuous. dac timing the AD7868 dac contains two latches, an input latch and a dac latch. data must be loaded to the input latch under the control of the tclk, tfs and dt serial logic inputs. data is then transferred from the input latch to the dac latch under the control of the ldac signal. only the data in the dac latch determines the analog output of the AD7868. data is loaded to the input latch under control of tclk, tfs and dt. the AD7868 dac expects a 16-bit stream of serial data on its dt input. data must be valid on the falling edge of tclk. the tfs input provides the frame synchronization sig- nal which tells the AD7868 dac that valid serial data will be available for the next 16 falling edges of tclk. figure 8 shows the timing diagram for the serial data format. although 16 bits of data are clocked into the input latch, only 12 bits are transferred into the dac latch. therefore, 4 bits in the stream are dont cares since their value does not affect the dac latch data. the bit positions are 4 dont cares followed by the 12-bit dac data starting with the msb. the ldac signal controls the transfer of data to the dac latch. normally, data is loaded to the dac latch on the falling edge of ldac . however, if ldac is held low, then serial data is loaded to the dac latch on the sixteenth falling edge of tclk. if ldac goes low during the loading of serial data to the input latch, no dac latch update takes place on the falling edge of ldac . if ldac stays low until the serial transfer is completed, then the update takes place on the sixteenth falling edge of tclk. if ldac returns high before the serial data transfer is completed, no dac latch update takes place. notes 1 external 4.7k w pull-up resistor 2 external 2k w pull-up resistor 3 continuous rclk (dashed line) when the control input = ?v and noncontinuous when the control input = 0v t 13 t 3 convst rfs 1 rclk 2, 3 dr 1 db11 db10 db9 db1 db0 conversion time t 1 t 5 t 2 t 4 t 6 figure 7. adc control timing diagram db11 db10 db1 db0 t 7 t 8 t 9 t 10 t 11 tfs tclk dt don't care don't care don't care don't care figure 8. dac control timing diagram
AD7868 C9C rev. b AD7868 dynamic specifications the AD7868 is specified and 100% tested for dynamic perfor- mance specifications as well as traditional dc specifications such as integral and differential nonlinearity. these ac specifications are required for signal processing applications such as speech recognition, spectrum analysis, and high-speed modems. these applications require information on the converters effect on the spectral content of the input signal. hence, the parameters for which the AD7868 is specified include snr, harmonic distor- tion and peak harmonics. these terms are discussed in more de- tail in the following sections. signal-to-noise ratio (snr) snr is the measured signal-to-noise ratio at the output of the adc or dac. the signal is the rms magnitude of the funda- mental. noise is the rms sum of all the nonfundamental signals up to half the sampling frequency (fs/2) excluding dc. snr is dependent upon the number of levels used in the quantization process; the more levels, the smaller the quantization noise. the theoretical signal-to-noise ratio for a sine wave input is given by snr = ( 6.02 n + 1.76) db (1) where n is the number of bits. thus for an ideal 12-bit con- verter, snr = 74 db. effective number of bits the formula given in equation 1 relates the snr to the number of bits. rewriting the formula, as in equation 2, it is possible to get a measure of performance expressed in effective number of bits (n). n = snr 1.76 6.02 (2) the effective number of bits for a device can be calculated di- rectly from its measured snr. harmonic distortion harmonic distortion is the ratio of the rms sum of harmonics to the fundamental. for the AD7868, total harmonic distortion (thd) is defined as thd = 20 log v 2 2 + v 3 2 + v 4 2 + v 5 2 + v 6 2 v 1 where v 1 is the rms amplitude of the fundamental and v 2 , v 3 , v 4 , v 5 and v 6 are the rms amplitudes of the second through to the sixth harmonic. the thd is also derived from the fft plot of the adc or dac output spectrum. adc testing the output spectrum from the adc is evaluated by applying a sine-wave signal of very low distortion to the v in input which is sampled at an 83 khz sampling rate. a fast fourier transform (fft) plot is generated from which the snr data can be ob- tained. figure 9 shows a typical 2048 point fft plot of the AD7868bq adc with an input signal of 10 khz and a sam- pling frequency of 83 khz. the snr obtained from this graph is 73 db. it should be noted that the harmonics are taken into account when calculating the snr. figure 10 shows a typical plot of effective number of bits versus frequency for an AD7868bq with a sampling frequency of 83 khz. the effective number of bits typically falls between 11.7 and 11.85 corresponding to snr figures of 72.2 and 73.1 db. figure 9. AD7868, adc fft plot 12 11.5 11 10.5 10 input frequency ?khz sample frequency = 83 khz t a = 25 c effective number of bits 0 41.5 figure 10. effective number of bits vs. frequency for the adc dac testing a simplified diagram of the method used to test the dynamic performance specifications of the dac is outlined in figure 11. data is loaded to the dac under control of the microcontroller and associated logic. the output of the dac is applied to a 9th order low-pass filter whose cutoff frequency corresponds to the nyquist limit. the output of the filter is in turn applied to a 16-bit accurate digitizer. this digitizes the signal and the micro- controller generates an fft plot from which the dynamic per- formance of the dac can be evaluated.
AD7868 C10C rev. b AD7868 dac low-pass filter 16-bit digitizer micro- controller figure 11. AD7868 dac dynamic performance test circuit the digitizer sampling is synchronized with the dac update rate to ease fft calculations. the digitizer samples the dac output after the output has settled to its new value. therefore, if the digitizer were to sample the output directly it would effec- tively be sampling a dc value each time. as a result, the dynamic performance of the dac would not be measured correctly. us- ing the digitizer directly on the dac output would give better results than the actual performance of the dac. using a filter between the dac and the digitizer means that the digitizer samples a continuously moving signal and the true dynamic per- formance of the AD7868 dac output is measured. figure 12 shows a typical 2048 point fast fourier transform plot for the AD7868 dac with an update rate of 83 khz and an output frequency of 1 khz. the snr obtained from the graph is 73 dbs. figure 12. AD7868 dac fft plot some applications will require improved performance versus fre- quency from the AD7868 dac. in these applications, a simple sample-and-hold circuit such as that outlined in figure 13 will extend the very good performance of the dac to 20 khz. other applications will already have an inherent sample-and-hold function following the AD7868 dac output. an example of this type of application is driving a switched-capacitor filter where the updating of the dac is synchronized with the switched-capacitor filter. this inherent sample-and-hold function also extends the frequency range performance. performance versus frequency the typical performance plots of figures 14 and 15 show the AD7868s dac performance over a wide range of input fre- quencies at an update rate of 83 khz. the plot of figure 14 is without a sample-and-hold on the dac output while the plot of figure 15 is generated with a sample-and-hold on the output. AD7868* ldac v out q adg201hs s1 d1 in1 ad711 *additional pins omitted for clarity r2 2k2 c9 330pf 1? one shot delay r1 2k2 ldac figure 13. dac sample-and-hold circuit t a = +25 c frequency ?khz 80 70 0 05 1 snr ?dbs 234 40 30 20 10 60 50 figure 14. dac performance vs. frequency (no sample- and-hold) t a = +25 c frequency ?khz 80 70 0 0 20 5 snr ?dbs 10 15 40 30 20 10 60 50 figure 15. dac performance vs. frequency (sample-and- hold)
AD7868 C11C rev. b microprocessor interfacing microprocessor interfacing to the AD7868 is via a serial bus that uses standard protocol compatible with dsp machines. the communication interface consists of separate transmit (dac) and receive (adc) sections whose operations can be either syn- chronous or asynchronous with respect to each other. each sec- tion has a clock signal, a data signal and a frame or strobe pulse. synchronous operation means that data is transmitted from the adc and to the dac at the same time. in this mode only one interface clock is needed and this has to be the adc clock out, so rclk must be connected to tclk. for asynchronous op- eration, dac and adc data transfers are independent of each other, the adc provides the receive clock (rclk) while the transmit clock (tclk) may be provided by the processor or the adc or some other external clock source. another option to be considered with serial interfacing is the use of a gated clock. a gated clock means that the device that is sending the data switches on the clock when data is ready to be transmitted and three states the clock output when transmission is complete. only 16 clock pulses are transmitted with the first data bit getting latched into the receiving device on the first fall- ing clock edge. ideally, there is no need for frame pulses, how- ever, the AD7868 dac frame input ( tfs ) has to be driven high between data transmissions. the easiest method is to use rfs to drive tfs and use only synchronous interfacing. this avoids the use of interconnects between the processor and AD7868 frame signals. not all processors have a gated clock facility, figure 16 shows an example with the dsp56000. table i below shows the number of interconnect lines between the processor and the AD7868 for the different interfacing op- tions. the AD7868 has the facility to use different clocks for transmitting and receiving data. this option, however, only ex- ists on some processors and normally just one clock (adc clock) is used for all communication with the AD7868. for sim- plicity, all the interface examples in this data sheet use synchro- nous interfacing and use the adc clock (rclk) as an input for the dac clock (tclk). for a better understanding of each of these interfaces, consult the relevant processor data sheet. table i. interconnect lines for different interfacing options no. of configuration interconnects signals synchronous 4 rclk, dr, dt and rfs (tclk = rclk, tfs = rfs ) asynchronous* 5 or 6 rclk, dr, rfs , dt, tfs (tclk = rclk or m p serial clk) synchronous 3 rclk, dr and dt gated clock (tclk = rclk, tfs = rfs ) *5 lines of interconnect when tclk = rclk 6 lines of interconnect when tclk = m p serial clk AD7868dsp56000 interface figure 16 shows a typical interface between the AD7868 and dsp56000. the interface arrangement is synchronous with a gated clock requiring only three lines of interconnect. the dsp56000 internal serial control registers have to be configured for a 16-bit data word with valid data on the first falling clock edge. conversion starts and dac updating are controlled by an external timer. data transfers, which occur during adc conver- sions, are between the processor receive and transmit shift regis- ters and the AD7868s adc and dac. at the end of each 16-bit transfer the dsp56000 receives an internal interrupt indi- cating the transmit register is empty and the receive register is full. dsp56000 std tfs *additional pins omitted for clarity dt sck srd rclk dr convst rfs timer AD7868* 4.7k w 2k w 4.7k w ldac control tclk 5v + sc0 figure 16. AD7868dsp56000 interface AD7868adsp-2101/adsp-2102 interface an interface which is suitable for the adsp-2101 or the adsp- 2102 is shown in figure 17. the interface is configured for syn- chronous, continuous clock operation. the ldac is tied low so the dac gets updated on the sixteenth falling clock after tfs goes low. alternatively ldac may be driven from a timer as shown in figure 16. as with the previous interface the processor receives an interrupt after reading or writing to the AD7868 and updates its own internal registers in preparation for the next data transfer. adsp-2101/ adsp-2102 tfs dt tclk dt ldac tfs *additional pins omitted for clarity rfs sclk dr rclk dr convst rfs control timer AD7868* 4.7k w 2k w 4.7k w 5v 5v + figure 17. AD7868adsp-2101/adsp-2102 interface
AD7868 C12C rev. b AD7868tms32020/tms320c25 interface figure 18 shows an interface which is suitable for the tms32020/tms320c25 processors. this interface is config- ured for synchronous, continuous clock operation. note, the AD7868 will not interface correctly to these processors if the AD7868 is configured for a noncontinuous clock. conversion starts and dac updating are controlled by an external timer. tms32020 tms320c25 fsx dx tclk dt tfs *additional pins omitted for clarity ldac fsr clkr dr rclk dr convst rfs control timer AD7868* 4.7k w 2k w 4.7k w 5v + 5v clkx figure 18. AD7868tms32020/tms320c25 interface application hints good printed circuit board (pcb) layout is as important as the circuit design itself in achieving high speed a/d performance. the AD7868s comparator is required to make bit decisions on an lsb size of 1.465 mv. to achieve this, the designer has to be conscious of noise both in the adc itself and in the preced- ing analog circuitry. switching mode power supplies are not rec- ommended as the switching spikes will feed through to the comparator causing noisy code transitions. other causes of con- cern are ground loops and digital feedthrough from micropro- cessors. these are factors which influence any adc, and a proper pcb layout which minimizes these effects is essential for best performance. layout hints ensure that the layout for the printed circuit board has the digi- tal and analog signal lines separated as much as possible. take care not to run any digital track alongside an analog signal track. guard (screen) the analog input with agnd. establish a single point analog ground (star ground) separate from the logic system ground as close as possible to the AD7868 agnd pins. connect all other grounds and the AD7868 dgnd to this single analog ground point. do not connect any other digital grounds to this analog ground point. low impedance analog and digital power supply common re- turns are essential to low noise operation of the adc, so make the foil width for these tracks as wide as possible. the use of ground planes minimizes impedance paths and also guards the analog circuitry from digital noise. the circuit layout of figures 22 and 23 have both analog and digital ground planes which are kept separated and only joined together at the AD7868 agnd pins. noise keep the input signal leads to v in and signal return leads from agnd as short as possible to minimize input noise coupling. in applications where this is not possible, use a shielded cable be- tween the source and the adc. reduce the ground circuit im- pedance as much as possible since any potential difference in grounds between the signal source and the adc appears as an error voltage in series with the input signal. input/output board figure 19 shows an analog i/o board based on the AD7868. the corresponding printed circuit board (pcb) layout and silkscreen are shown in figures 21 to 23. the analog input to the AD7868 is buffered with an ad711 op amp. there is a component grid provided near the analog input on the pcb which may be used for an antialiasing filter for the adc or a reconstruction filter for the dac or any other condi- tioning circuitry. to facilitate this option, there are two wire links (labeled lk1 and lk2) required on the analog input and output tracks. the board contains a sha circuit which can be used on the output of the AD7868 dac to extend the very good perfor- mance of the part over a wider frequency range. the increased performance from the sha can be seen in figures 14 and 15 of this data sheet. a wire link (labeled lk3) connects the board output to either the sha output or directly to the AD7868 dac output. there are three ldac link options on the board; ldac can be driven from an external source independent of convst , ldac can be tied to convst or ldac can be tied to gnd. choosing the latter option of tying ldac to gnd disables the sha operation, and places the sha permanently in the track mode. microprocessor connections to the board are made by a 9-way d-type connector. the pinout is shown in figure 20. the adcs digital outputs are buffered with 74hc4050s. these buffers provide a higher current output capability for high capacitance loads or cables. normally, these buffers are not required as the AD7868 will be sitting on the same board as the processor. power supply connections the pcb requires two analog power supplies and one 5 v digi- tal supply. connections to the analog supply are made directly to the pcb as shown on the silkscreen in figure 21. the con- nections are labeled v+ and vC and the range for both of these supplies is 12 v to 15 v. connections to the 5 v digital supply are made through the d-type connector skt6. the 5 v ana- log supply required by the AD7868 are generated from two volt- age regulators on the v+ and vC supplies.
AD7868 C13C rev. b in out gnd 5v v+ ic5 78l05 c2 0.1 m f c23 10 m f dgnd v in v dd ldac convst in out gnd v ro adc ri dac ro dac control clk agnd dgnd rclk dr tclk rfs tfs dt 5v lk1 lk4 a b c a b c lk5 lk6 a b c lk7 lk8 ad711 analog input 3v range analog output 3v range lk2 v ss component grid lk3 a b c a b c a b c ab c ic2 skt1 skt2 ldac skt3 convst skt4 a b clr 5v c ext q 5v gnd ic8 1/2 74hc221 agnd r3 4.7k w r4 2k w r5 4.7k w 5v dr rclk rfs tfs tclk dt dgnd skt6 9-way d-type connector lk9 ic7 1/2 74hc4050 skt5 ext clk ic6 79l05 + c6 0.1 m f c5 10 m f c8 0.1 m f c7 10 m f v out c4 0.1 m f c3 10 m f component grid c10 0.1 m f c9 10 m f v + ad711 ic3 + v c12 0.1 m f c11 10 m f ic4 adg201hs r1 2k w c21 330pf r ext /c ext ic1 AD7868 c24 0.1 m f r7 200 c1 10 m f r6 15k c22 68pf ?v ?v ?v v v ss v cc v dd v+ r2 2k w figure 19. input/output circuit based on the AD7868 24 3 15 6789 rclk tclk dt dr dgnd nc 5v tfs rfs nc = no connect figure 20. skt6, d-type connector pinout wire link options lk1, analog input link lk1 connects the analog input to a component grid or to a buffer amplifier which drives the adc input. lk2, analog output link lk2 connects the analog output to the component grid or to either the sha or dac output (see lk3). lk3, sha or dac select the analog output may be taken directly from the dac or from a sha at the output of the dac.
AD7868 C14C rev. b lk4, dac reference selection the dac reference may be connected to either the adc refer- ence output (ro adc) or to the dac reference (ro dac). lk5, adc internal clock selection this link configures the adc for continuous or noncontinuous internal clock operation. lk6, dac updating the dac, ldac input may asserted independently of the adc convst signal or it may be tied to convst or it may tied to gnd. lk7, adc clock source this link provides the option for the adc to use its own inter- nal clock oscillator or an external ttl compatible clock. lk8 frame synchronous option lk8 provides the option of tying the adc rfs output to the dac tfs input. lk9 transmit/receive clock option lk9 provides the option to connect the adc rclk to the dac tclk. component list ic1 AD7868 ic2, ic3 2x ad711 ic4, adg201hs ic5, mc78l05 ic6, mc79l05 ic7, 74hc4050 ic8, 74hc221 c1, c3, c5, c7 c9, c11, c13, c15 10 m f capacitor c17, c19, c23 c2, c4, c6, c8 c10, c12, c14, c16 0.1 m f capacitor c18, c20, c24 c21 330 pf capacitor c22 68 pf capacitor r1, r2, r4 2 k w resistor r3, r5 4.7 k w resistor r6 15 k w resistor r7 200 w resistor lk1, lk2, lk3, lk4, lk5, lk6, lk7, lk8 shorting plugs lk9 skt1, skt2, skt3, skt4, skt5 bnc sockets skt6 9-contact d-type connector figure 21. silkscreen for the circuit diagram of figure 19
AD7868 C15C rev. b figure 22. component side layout for the circuit diagram of figure 19 figure 23. solder side layout for the circuit diagram of figure 19
AD7868 C16C rev. b outline dimensions dimensions shown in inches and (mm). c1410C10C7/90 printed in u.s.a. 24-pin plastic (n-24) 24-pin cerdip (q-24) 28-pin plastic soic (r-28)

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